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ASIC Design Flow



Very Large Scale Integration of electronic components has enabled development of smaller, faster, cheaper and sophisticated electronic devices. This has led to an unprecedented demand for complex Integrated circuits (ICs) on a single chip. These Application Specific Integrated Circuits or ASICs contain millions of transistors configured and optimized to address customers' unique requirements.

 A typical ASIC is designed at various abstraction levels:

  • Register Transfer
  • Logic Synthesis
  • Physical Design 

The corresponding verification steps for each abstraction level are:

  • RTL Verification
  • Logical Equivalence Check (and Timing Analysis)
  • Physical Verification (and Timing Analysis)

Once the design is verified against functional, timing, and foundry-specific requirements, it is taped out and sent for fabrication in the GDSII format.

This course walks you through these different stages of designing an ASIC - from specification to layout generation and tapeout. The unique blended-learning approach reinforces concepts at every stage through during e-learning and further provides training in the application of concepts through project work in trainer-led labs.

After completing this course, you will be able to:

  • Use ASIC terminologies during interactions with peers
  • Select the most appropriate ASIC design-methodologies for a given application 
  • Describe various steps used in designing an ASIC
  • Identify interaction between various ASIC design stages and optimize your design

Specialization Areas

 This course is part of the following VLSI specializations.

 ASIC-Timing Closure

  • Logic Design for VLSI Engineers
  • RTL Design using Verilog HDL
  • ASIC Design Flow 
  • Fundamentals of Static Timing Analysis
  • Advanced Static Timing Analysis

Analog Layout  

  • ASIC Design Flow  
  • Analog Circuit and Layout Design

Course structure and duration 

An e-Learning Component 

  • Lectures, topic-level assessments, guided practice problems
  • Course Run Time: 15 hours
  • Recommended Learning Time: 30-55 hours

Note: We strongly encourage learners to spend no more than 1-2 hours per day over 2-3 weeks.

Hands-on Instructor-Led Labs  

  • Concepts and project work using EDA tools
  • Run Time: 14-16 hours (2 days)

Note: You must complete eLearning prior to the lab session.

End of Course Assessment 

  • Online multiple-choice test
  • Run-time: 1 hour


Upon successful completion, you will earn an IEEE 'Certificate of Completion'. 

Target Audience

  • UG/PG students interested in a career in Digital Electronics or VLSI
  • New employees working in the field of VLSI design (frontend/backend)
  • Managers who are new to supervising VLSI design teams
  • Employees seeking to move to a lateral entry position in VLSI domains


  • Knowledge of fundamentals in Digital Electronics. 
  • Basic knowledge of Semiconductor Physics  

Course Fee

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* Fee is different for Collegs, Students and Corporations.

Lab Schedules

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